Title :
Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS
Author :
Bhargava, Mudit ; Cakir, Cagla ; Mai, Ken
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
We demonstrate the efficacy and associated costs of three reliability enhancing techniques for bi-stable PUF designs (SRAM and sense amplifier-based) - directed accelerated aging, multiple evaluations, and activation control. Measured results from a 65nm bulk CMOS full custom PUF testchip demonstrate that these technique are able to reduce the percentage of unreliable bits by up to 40%, 83%, and 71% respectively.
Keywords :
CMOS memory circuits; SRAM chips; ageing; amplifiers; integrated circuit design; integrated circuit reliability; integrated circuit testing; CMOS full custom PUF test chip; SRAM; activation control; bistable PUF reliability enhancement; physical unclonable function design; reliability enhancing techniques; sense amplifier-based directed accelerated aging; size 65 nm; Accelerated aging; Integrated circuit reliability; MOS devices; Noise; Random access memory;
Conference_Titel :
Hardware-Oriented Security and Trust (HOST), 2012 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-2341-3
DOI :
10.1109/HST.2012.6224314
