• DocumentCode
    2401692
  • Title

    FPGA based trustworthy authentication technique using Physically Unclonable Functions and artificial intelligence

  • Author

    Pappala, Swetha ; Niamat, Mohammed ; Sun, Weiqing

  • fYear
    2012
  • fDate
    3-4 June 2012
  • Firstpage
    59
  • Lastpage
    62
  • Abstract
    Field Programmable Gate Arrays (FPGAs) need built-in security not only to prevent reverse engineering, but also to prevent hacking and cloning while reconfiguring or partially reconfiguring the devices. To counter such threats, methodologies for preventing IC piracy have been developed that require a unique signature key for every fabricated chip. Physically Unclonable Functions (PUFs) can be used for such signature generation. This paper presents a design for cryptographic applications that can be implemented on an FPGA taking advantage of its unique architecture. The research is divided into three parts: The first part of the research involves development of techniques for the generation of uniquely distinguishable responses from Ring Oscillator PUFs. The second part involves development of error correction technique using Artificial Neural Networks. The third part involves a hashing function to redress the response bits. The proposed design is implemented on several Xilinx Spartan FPGAs and the Hamming distances for the responses are computed and analyzed. The uniqueness of the responses is found to be 49.0625%. It is also found that the results of the proposed error correction code are computationally efficient as compared to the conventional BCH codes.
  • Keywords
    cryptography; digital signatures; error correction codes; field programmable gate arrays; neural nets; BCH codes; FPGA based trustworthy authentication technique; Hamming distances; IC piracy; Xilinx Spartan FPGA; artificial intelligence; artificial neural networks; built-in security; cloning; cryptographic applications; error correction code; error correction technique; fabricated chip; field programmable gate arrays; hacking; hashing function; physically unclonable functions; response bits; reverse engineering; ring oscillator PUF; signature generation; signature key; Error correction; Error correction codes; Field programmable gate arrays; Multiplexing; Ring oscillators; Table lookup; Vectors; Cryptography; Error Correcting Code; FPGA; Neural Network; PUF; Security;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware-Oriented Security and Trust (HOST), 2012 IEEE International Symposium on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4673-2341-3
  • Type

    conf

  • DOI
    10.1109/HST.2012.6224320
  • Filename
    6224320