t-Private logic synthesis on FPGAs

A t-private circuit reveals no information about any internal logic node with up to t probes each cycle. In this paper, we propose efficient t-private logic design schemas. Note that these t probes pose a more powerful adversary than a side-channel attack. We develop tail-recursive t-private circuits based on AND-XOR networks. The tail-recursive t-private circuits are especially well-suited for FPGA LUT implementations. We implement simple adders using t-private tail-recursive logic synthesis on FPGA. Compared to the original t-private circuit model, our model reduces area by 50% and delay by 33% for FPGA implementations.