• DocumentCode
    2401774
  • Title

    Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure

  • Author

    Lamech, Charles ; Plusquellic, Jim

  • Author_Institution
    ECE Dept., Univ. of New Mexico, Albuquerque, NM, USA
  • fYear
    2012
  • fDate
    3-4 June 2012
  • Firstpage
    75
  • Lastpage
    82
  • Abstract
    The horizontal dissemination of the chip fabrication industry has raised new concerns over Integrated Circuit (IC) Trust, in particular, the threat of malicious functionality, i.e., a Hardware Trojan, that is added by an adversary to an IC. In this paper, we propose the use of a high-precision, low-overhead embedded test structure for measuring path delays to detect the delay anomalies introduced by hardware Trojans. The proposed test structure, called REBEL, is minimally invasive to the design as it leverages the existing scan structures. In this work, we integrate REBEL into a structural description of a pipelined Floating Point Unit. Trojan emulation circuits, designed to model internal wire loads introduced by a hardware Trojan, are inserted into the design at multiple places. The emulation cell incorporates an analog control pin to allow a variety of hardware Trojan loading scenarios to be investigated. We evaluate the detection sensitivity of REBEL for detecting hardware Trojans using regression analysis and hardware data collected from 62 copies of the chip fabricated in 90nm CMOS technology.
  • Keywords
    CMOS logic circuits; delay circuits; embedded systems; integrated circuit design; integrated circuit measurement; integrated circuit testing; pipeline processing; regression analysis; CMOS technology; IC trust; REBEL; Trojan emulation circuit design; analog control pin; chip fabrication industry; delay anomaly detection; detection sensitivity; hardware Trojan detection; hardware Trojan loading; high-precision low-overhead embedded test structure; horizontal dissemination; integrated circuit trust; internal wire load modeling; malicious functionality threat; path delay measurement; pipelined floating point unit; regional delay behavior; regression analysis; structural description; Security; Embedded Test Structure; Hardware Trojans; Path Delay; Regression Analysis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware-Oriented Security and Trust (HOST), 2012 IEEE International Symposium on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4673-2341-3
  • Type

    conf

  • DOI
    10.1109/HST.2012.6224324
  • Filename
    6224324