• DocumentCode
    2401785
  • Title

    Reverse engineering circuits using behavioral pattern mining

  • Author

    Li, Wenchao ; Wasson, Zach ; Seshia, Sanjit A.

  • fYear
    2012
  • fDate
    3-4 June 2012
  • Firstpage
    83
  • Lastpage
    88
  • Abstract
    Systems are increasingly being constructed from off-the-shelf components acquired through a globally distributed, untrusted supply chain. The lack of trust in these components necessitates additional validation of the components before use. Additionally, hardware trojans are becoming a pressing concern. In this paper, we present a novel formalism and method to systematically derive the highlevel function of an unknown circuit component given its gate-level netlist. We define the highlevel description of a circuit as an interconnection of instantiations of abstract library components characterized using logical specifications. The proposed approach is based on mining interesting behavioral patterns from the simulation traces of a gate-level netlist, and representing them as a pattern graph. A similar pattern graph is also generated for library components. Our method first computes input-output signal correspondences via subgraph isomorphism on the pattern graphs. The general function of the unknown circuit is then determined by finding the closest match in the component library, by model checking the unknown circuit against each logical specification. We demonstrate the effectiveness of our approach on publicly-available circuits.
  • Keywords
    circuit simulation; data mining; formal specification; formal verification; graph theory; reverse engineering; abstract library components; behavioral pattern mining; component validation; gate-level netlist; globally distributed untrusted supply chain; hardware trojans; high-level circuit component function; high-level circuit description; input-output signal correspondences; library components; logical specifications; model checking; pattern graph representation; reverse engineering circuits; subgraph isomorphism; Abstracts; Cost accounting; Hardware; Integrated circuit modeling; Libraries; Protocols; Reverse engineering;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Hardware-Oriented Security and Trust (HOST), 2012 IEEE International Symposium on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    978-1-4673-2341-3
  • Type

    conf

  • DOI
    10.1109/HST.2012.6224325
  • Filename
    6224325