DocumentCode :
2401846
Title :
Performance metrics and empirical results of a PUF cryptographic key generation ASIC
Author :
Meng-Day Yu ; Sowell, R. ; Singh, A. ; M´Raihi, D. ; Devadas, S.
Author_Institution :
Verayo, Inc., San Jose, CA, USA
fYear :
2012
fDate :
3-4 June 2012
Firstpage :
108
Lastpage :
115
Abstract :
We describe a PUF design with integrated error correction that is robust to various layout implementations and achieves excellent and consistent results in each of the following four areas: Randomness, Uniqueness, Bias and Stability. 133 PUF devices in 0.13 μm technology encompassing seven circuit layout implementations were tested. The PUF-based key generation design achieved less than 0.58 ppm failure rates with 50%+ stability safety margin. 1.75M error correction blocks ran error-free under worst-case V/T corners (±10% V, 125°C/-65°C) and under voltage extremes of ±20% V. All PUF devices demonstrated excellent NIST-random behavior (99 cumulative percentile), a criterion used to qualify random sources for use as keying material for cryptographic-grade applications.
Keywords :
application specific integrated circuits; cryptography; error correction; integrated circuit layout; ASIC; circuit layout; cryptographic key generation; error correction blocks; integrated error correction; key generation design; physical unclonable function; size 0.13 mum; Application specific integrated circuits; Circuit stability; Cryptography; Error correction; Layout; NIST; Oscillators; ASIC; Error Correction; Key Generation; NIST Randomness; Physical Unclonable Function (PUF);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Hardware-Oriented Security and Trust (HOST), 2012 IEEE International Symposium on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4673-2341-3
Type :
conf
DOI :
10.1109/HST.2012.6224329
Filename :
6224329
Link To Document :
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