DocumentCode
2402364
Title
RISC performance pushes back: A perspective on performance limits in general-purpose applications
Author
Johnson, Mike
Author_Institution
Adv. Micro Devices, Austin, TX, USA
fYear
1990
fDate
Feb. 26 1990-March 2 1990
Firstpage
241
Lastpage
245
Abstract
Reduced-instruction-set-computer (RISC) processors are positioned to extend performance in the application domain of general-purpose complex-instruction-set-computer (CISC) processors. These applications are less performance demanding and more cost sensitive than scientific applications, and so are subject to very different cost/performance tradeoffs. Exploring performance limits in general-purpose applications helps reveal the probably development of RISC microprocessors over the next several years. The primary limitation does not appear to be raw clock speed, but rather the speed of communication with the main memory. Superscalar techniques can help performance growth for about two processor generations. There are two alternatives for improving performance in the future: decrease the number of instructions executed and/or increase the instruction-execution rate. Both alternatives are examined in view of the performance benefits and costs. This reveals the path that processor developments are likely to take over the next few years.<>
Keywords
microprocessor chips; performance evaluation; reduced instruction set computing; RISC performance; general-purpose complex-instruction-set-computer; microprocessors; performance limits; Clocks; Computer architecture; Costs; Encoding; Hardware; High level languages; Instruction sets; Microprocessors; Optimizing compilers; Reduced instruction set computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-2028-5
Type
conf
DOI
10.1109/CMPCON.1990.63683
Filename
63683
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