On-line diagnosis and reconfiguration of FPGA systems

Fault tolerance is becoming an important issue for the effective use of FPGA-based architectures in mission-critical applications. This paper introduces an innovative approach to design FPGA systems with on-line diagnosis and reconfiguration, at a limited cost in terms of FPGA redundant resources and interconnections. The technique is based on high-level synthesis of the self-checking datapath to be mapped on the FPGA. The analysis of the computation flow allows for location of the necessary checking points. Scheduling is performed in order to minimize the circuit complexity, while satisfying the maximum latency allowed by the application. Allocation is performed as a suited trade-off between the circuit complexity and the reconfiguration efficiency. Problems and constraints due to re-use of units in different points of the computation are taken into account. The faulty block replacement policy is discussed, together with its implication in terms of re-use and of interconnection re-routing