Title :
Design and simulation of high level low power 7T SRAM cell using various process & circuit techniques
Author :
Mishra, Shipra ; Dubey, Amit ; Tomar, Shelendra Singh ; Akashe, Shyam
Author_Institution :
VLSI Design, ITM Univ., Gwalior, India
Abstract :
Low power memory is required today most priority with also high stability. The power is most important factor for today technology so the power reduction for one cell is vital role in memory design techniques. In this paper we introduced some design circuit techniques for low power design. Leakage current in standby mode is the major part of power loss. We concentrate on the technique that to reduced the leakage current in standby mode.
Keywords :
SRAM chips; leakage currents; low-power electronics; design circuit techniques; high level low power 7T SRAM cell; high stability; leakage current; low power memory; power loss; standby mode; CMOS integrated circuits; Leakage current; Logic gates; MOSFETs; Random access memory; Threshold voltage; CMOS; Circuit techniques; Process Technique; SRAM; Threshold Voltage;
Conference_Titel :
Signal Processing, Computing and Control (ISPCC), 2012 IEEE International Conference on
Conference_Location :
Waknaghat Solan
Print_ISBN :
978-1-4673-1317-9
DOI :
10.1109/ISPCC.2012.6224371
