The 68040 on-chip memory subsystem

The Motorola 68040 is a third-generation, high-performance, full 32-b microprocessor. The caches, memory-management units (MMUs), and autonomous controllers for the caches and external bus that comprise the memory subsystem are described. The 68040´s memory subsystem supports the performance of the integer and floating-point units by using autonomous internal cache/MMU controllers in a Harvard architecture. Physical caches of 4 kB each for instruction and data are provided. The data cache operates in copyback or write-through mode on a per-page basis. Combined with each cache is a separate address translation cache of 64 entries and two transparent translation registers that operate in parallel with the cache to provide complete memory management in a virtual, demand-page environment. The memory subsystem is designed to provide the majority of the required memory bandwidth for the internal caches. The 68040 has two MMUs: one for instruction logical-to-physical address translation and one for data address translation. High performance is possible owing in part to the high level of concurrency available in the memory subsystem.<>