DocumentCode
2402879
Title
iDDT test methodologies for very deep sub-micron CMOS circuits
Author
Chehab, Ali ; Makki, Rafic ; Spica, Michael ; Wu, David
fYear
2002
fDate
2002
Firstpage
403
Lastpage
407
Abstract
In this paper, we investigate three iDDT-based test methodologies, Double Threshold iDDT, Delta iDDT, and Delayed iDDT, and we compare their effectiveness in the detection of defects in very deep sub-micron random logic circuits. The target defects are resistive opens and resistive bridges. We present preliminary simulation results of 49 defects to study the defect sensitivity of each of the three test methods. This paper reports our preliminary results on these three test methods using a relatively small transistor-level sample circuit, and is not intended to imply any feasibility in a production environment. The test methods presented herein are the subject of a current invention disclosure
Keywords
CMOS logic circuits; fault simulation; integrated circuit testing; logic testing; 0.35 micron; 3.3 V; defect detection; defect sensitivity; delayed iDDT; delta iDDT; double threshold iDDT; iDDT test methodologies; power supply voltage; random logic circuits; resistive bridges; resistive opens; simulation results; transistor-level sample circuit; very deep sub-micron CMOS circuits; CMOS technology; Circuit faults; Circuit simulation; Circuit testing; Integrated circuit interconnections; Logic circuits; Power supplies; Semiconductor device testing; Upper bound; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on
Conference_Location
Christchurch
Print_ISBN
0-7695-1453-7
Type
conf
DOI
10.1109/DELTA.2002.994659
Filename
994659
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