On C-testability of carry free dividers

Author

Aziz, S.M. ; Carr, S.J.

Author_Institution

Sch. of Electr. & Inf. Eng., Univ. of South Australia, Mawson Lakes Campus´´, SA, Australia

fYear

2002

fDate

2002

Firstpage

417

Lastpage

421

Abstract

This paper examines the C-testability of a carry-free divider architecture that uses a radix-2 number system. This divider is extremely fast in comparison to the traditional carry-propagate method of division. It has a computational time of the order of O(W), while carry-propagate division has a time of the order of O(W). The results of the investigation presented here show that the architecture requires the addition of a significant amount of logic circuitry for correct functionality and uniformity of the inputs and outputs. This paper presents the logic blocks required to turn the architecture into one that can be implemented in hardware and examines the effects of these changes on the computation time and testability

Keywords

circuit complexity; digital arithmetic; dividing circuits; logic arrays; logic testing; C-testability; carry-free divider architecture; computational time; divider array; functionality; input uniformity; logic blocks; logic circuitry; output uniformity; radix-2 number system; Australia; Circuit analysis; Circuit testing; Computer architecture; Encoding; Equations; Hardware; Lakes; Logic circuits; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Conference_Location

Christchurch

Print_ISBN

0-7695-1453-7

Type

conf

DOI

10.1109/DELTA.2002.994662

Filename

994662