Title :
Modifying test vectors for reducing power dissipation in CMOS circuits
Author :
Higami, Yoshinobu ; Kobayashi, Shin-ya ; Takamatsu, Yuzo
Author_Institution :
Dept. of Comput. Sci., Ehime Univ., Matsuyama, Japan
Abstract :
This paper presents a method to modify test vectors for reducing power dissipation in CMOS sequential circuits. Test vectors are modified by inverting values of primary inputs one by one. With respect to the reduction of power dissipation, we check if the average number of signal transition gates is decreased and if the maximum number of signal transition gates is not increased. Original fault coverage is guaranteed by logic simulation and fault simulation. The effectiveness of the proposed method is shown by experimental results for ISCAS´89 benchmark circuits
Keywords :
CMOS logic circuits; fault simulation; integrated circuit testing; logic simulation; logic testing; sequential circuits; CMOS sequential circuit; fault coverage; fault simulation; logic simulation; power dissipation; signal transition gate; test vector; Benchmark testing; Capacitance; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Logic testing; Power dissipation; Sequential analysis;
Conference_Titel :
Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on
Conference_Location :
Christchurch
Print_ISBN :
0-7695-1453-7
DOI :
10.1109/DELTA.2002.994665
