Abacus: a 1024 processor 8 ns SIMD array

Author

Bolotski, M. ; Simon, T. ; Vieri, C. ; Amirtharajah, R. ; Knight, T.F., Jr.

Author_Institution

Artificial Intelligence Lab., MIT, Cambridge, MA, USA

fYear

1995

fDate

27-29 Mar 1995

Firstpage

28

Lastpage

40

Abstract

Describes the Abacus machine at a number of levels. Presents the microarchitecture of the PE comprising the reconfigurable bit-parallel array, a set of arithmetic and communication primitives, details of the VLSI implementation, and system-level design issues of a high-speed SIMD array. The most concrete goal of the Abacus project was to design and build a machine that could be used by members of the MIT Artificial Intelligence Laboratory for real-time early vision processing. Along the way, we explored several architectural ideas

Keywords

VLSI; bit-slice computers; computer vision; parallel architectures; real-time systems; reconfigurable architectures; 8 ns; Abacus; SIMD array; VLSI implementation; bit-slice processing element; communication primitives; microarchitecture; real-time early vision processing; reconfigurable bit-parallel array; system-level design issues; Arithmetic; Artificial intelligence; Computer architecture; Control systems; Hardware; Laboratories; Log periodic antennas; Process control; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in VLSI, 1995. Proceedings., Sixteenth Conference on

Conference_Location

Chapel Hill, NC

Print_ISBN

0-8186-7074-9

Type

conf

DOI

10.1109/ARVLSI.1995.515609

Filename

515609