Title :
Minimization and partitioning method reducing input sets
Author :
Hlavicka, Jan ; Fiser, Petr
Author_Institution :
Czech Tech. Univ., Prague, Czech Republic
Abstract :
The article describes a new Boolean minimization and single-level partitioning method based on the BOOM minimization system. The minimization is performed with respect to the restrictions stated for the number of inputs and outputs of individual components and/or with the goal to reach load balancing for the inputs. The method can handle extremely large functions (up to thousands of input variables) in a very short time and its use is advantageous above all for highly, unspecified functions, where the number of don´t cares is large
Keywords :
Boolean functions; logic partitioning; minimisation of switching nets; BOOM minimization system; Boolean minimization; input set; logic circuit design; single-level partitioning; Boolean functions; Electronics packaging; Field programmable gate arrays; Input variables; Load management; Logic circuits; Logic gates; Minimization methods; Propagation delay; Table lookup;
Conference_Titel :
Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on
Conference_Location :
Christchurch
Print_ISBN :
0-7695-1453-7
DOI :
10.1109/DELTA.2002.994666
