A flexible embedded SRAM compiler

Author

Liu, Yong ; Gao, Zhiqiang ; He, Xiangqing

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2002

fDate

2002

Firstpage

474

Lastpage

476

Abstract

SRAM compiler uses predefined building blocks or leaf cells and connectivity information to compile SRAMs of user-specified size. In this paper, a high-speed embedded SRAM compiler is described. It is based on TSMC´s 0.5 μm CMOS process. It can compile both single-port and dual-port SRAMs. SRAM is a completely synchronous architecture with a maximal capacity 16k×64=1 Mb bits. The compiler generates the layout, behavioral level models, schematic symbols, and a layout abstraction to place and route. The program in Skill language can automatically complete the creation of all the models in different levels. The SRAM compiler has a friendly user interface. Users can specify the necessary parameters and then get all the results. The SRAM compiler can be easily integrated into Cadence and other CAD frameworks

Keywords

CMOS memory circuits; SRAM chips; cellular arrays; circuit CAD; integrated circuit design; multiport networks; 0.5 micron; 1 Mbit; CAD frameworks; CMOS; Cadence; Skill language; behavioral level models; connectivity information; dual-port SRAMs; flexible embedded SRAM compiler; high-speed embedded compiler; layout abstraction; leaf cells; predefined building blocks; schematic symbols; single-port SRAMs; synchronous architecture; user interface; user-specified size; CMOS process; Communication system control; Decoding; Digital signal processing chips; Helium; Logic testing; Microelectronics; Random access memory; Semiconductor device modeling; User interfaces;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Conference_Location

Christchurch

Print_ISBN

0-7695-1453-7

Type

conf

DOI

10.1109/DELTA.2002.994676

Filename

994676