Automatic synthesis of gate-level timed circuits with choice

This paper presents a CAD tool for the automatic synthesis of gate-level timed circuits from general specifications to basic gates such as AND gates, OR gates, and C-elements. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize the design. Our procedure begins with a textual specification capable of specifying conditional operation, or choice. This specification is systematically transformed to a graphical representation which can be analyzed using an exact and efficient timing analysis algorithm to find the reachable stale space. From this state space, a timed circuit that is hazard-free at the gate-level is derived, facilitating the use of semi-custom components, such as standard-cells and gate-arrays. Because timing information is used to guide the synthesis to reduce circuit complexity while guaranteeing correct operation, the resulting timed circuit implementations are up to 40 percent smaller and 50 percent faster than those produced using other design methodologies