A RISC development case study

The VL86C020 is a second-generation reduced-instruction-set-computer (RISC) processor that is upwardly software compatible with the VL86C010. The latest family member incorporates a 4-kB on-chip cache memory to increase performance and lower memory bandwidth demands. Since multiprocessor systems are now feasible, a new semaphore instruction has been added to assist in shared resource allocation. In this case study the development of this family of RISC devices from concept to implementation is examined. By offering the CPU and cache memory on a single device, and itself as a core, the processor offers a superior upward migration path because the highest frequency memory path is not required to cross a chip boundary. As process rules continue to shrink, the clock frequency can be increased for on-chip operations accordingly without undue demands on the external memory system bandwidth.<>