DocumentCode
2403302
Title
A self-scaling neural hardware structure that reduces the effect of some implementation errors
Author
Djahanshahi, H. ; Ahmadi, M. ; Jullien, G.A. ; Miller, W.C.
Author_Institution
Dept. of Electr. Eng., Windsor Univ., Ont., Canada
fYear
1997
fDate
24-26 Sep 1997
Firstpage
588
Lastpage
597
Abstract
This paper explores a neural network hardware structure with distributed neurons that exhibits useful properties of self-scaling and averaging. In conventional sigmoidal neural networks with lumped neurons, the effects of weight errors and mismatches become more noticeable at the output as the network becomes larger. It is shown here that based on a stochastic model the inherent scaling property of a distributed neuron structure controls the output noise (error) to signal ratio as the number of inputs to an Adaline increases. Moreover, the averaging effect of distributed elements minimizes characteristic variations among neurons. These properties altogether provides a robust hybrid hardware with digital synaptic weights and analog neurons. A VLSI realization and an application of this neural structure are explained
Keywords
CMOS integrated circuits; VLSI; hybrid integrated circuits; neural chips; Adaline; VLSI realization; analog neurons; averaging; digital synaptic weights; distributed neurons; implementation errors; robust hybrid hardware; self-scaling neural hardware structure; stochastic model; Analog-digital conversion; Distributed control; Error correction; Fabrication; Neural network hardware; Neural networks; Neurons; Signal to noise ratio; Stochastic resonance; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks for Signal Processing [1997] VII. Proceedings of the 1997 IEEE Workshop
Conference_Location
Amelia Island, FL
ISSN
1089-3555
Print_ISBN
0-7803-4256-9
Type
conf
DOI
10.1109/NNSP.1997.622441
Filename
622441
Link To Document