A synthesisable VHDL model for an easily testable generalised multiplier

This paper presents a synthesisable VHDL model for a generalised multiplier capable of performing multiplication of both sign-magnitude and two´s complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand word-lengths thereby reducing automatic test generation, simulation and testing times. The model has been used successfully for generating multiplier macros of various operand lengths in different target technologies. A test generation program has been developed for, automatic generation of vectors of variable lengths