A synthesisable VHDL model for an easily testable generalised multiplier

Author

Aziz, S.M. ; Basheer, C.N. ; Kamruzzaman, J.

Author_Institution

Sch. of Electr. & Inf. Eng, Univ. of South Australia, Mawson Lakes, SA, Australia

fYear

2002

fDate

2002

Firstpage

504

Lastpage

506

Abstract

This paper presents a synthesisable VHDL model for a generalised multiplier capable of performing multiplication of both sign-magnitude and two´s complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand word-lengths thereby reducing automatic test generation, simulation and testing times. The model has been used successfully for generating multiplier macros of various operand lengths in different target technologies. A test generation program has been developed for, automatic generation of vectors of variable lengths

Keywords

automatic testing; digital arithmetic; hardware description languages; logic testing; multiplying circuits; automatic generation; automatic test generation; generalised multiplier; multiplier macros; operand lengths; sign-magnitude operands; synthesisable VHDL model; test generation program; test vectors; testing times; two´s complement operands; variable length vectors; Australia; Automatic testing; Circuit testing; Digital signal processors; Electronic equipment testing; Information technology; Lakes; Logic; Signal processing algorithms; Signal synthesis;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Applications, 2002. Proceedings. The First IEEE International Workshop on

Conference_Location

Christchurch

Print_ISBN

0-7695-1453-7

Type

conf

DOI

10.1109/DELTA.2002.994685

Filename

994685