A 33-ns 64-Mb DRAM with Master-Wordline Architecture

Author

Galbi, Duane ; Althoff, Klaus ; Parent, Rich ; Kiehl, Oliver ; Houghton, Russ ; Bonner, Fergal ; Killian, Mike ; Wilson, Adam ; Lau, Klaus ; Clinton, Mike ; Chapman, Dave ; Fischer, Horst

Author_Institution

IBM Technol. Products, Essex Junction, VT, USA

fYear

1992

fDate

21-23 Sept. 1992

Firstpage

131

Lastpage

134

Abstract

A 33-ns 64-Mb DRAM with a master-wordline architecture that allows for wordline boosting has been successfully designed and fabricated. The master-wordline scheme incorporates a high-threshold PFET which enables the boost voltage to be controlled by standard CMOS levels. The high-threshold PFET also generates a stable low-power reference voltage for the boost system.

Keywords

CMOS memory circuits; field effect transistors; random-access storage; CMOS; DRAM; boost system; high-threshold PFET; low-power reference voltage; master-wordline architecture; wordline boosting; Boosting; CMOS technology; Capacitance; Decoding; Driver circuits; Random access memory; Reservoirs; Surface resistance; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1992. ESSCIRC '92. Eighteenth European

Conference_Location

Copenhagen

Print_ISBN

87-984232-0-7

Type

conf

DOI

10.1109/ESSCIRC.1992.5468392

Filename

5468392

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2403622