DocumentCode :
2403912
Title :
Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics
Author :
Cai, X. ; Nabors, K. ; White, J.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fYear :
1995
fDate :
27-29 Mar 1995
Firstpage :
200
Lastpage :
211
Abstract :
This paper describes an efficient implementation of a Galerkin based multipole-accelerated boundary element method for 3-D capacitance extraction of conductors in an arbitrary piecewise-constant dielectric medium. Results are presented to demonstrate that the Galerkin method is substantially more accurate than the commonly used collocation scheme for problems with dielectric interfaces. In addition, it is shown experimentally that for a given discretization, a careful implementation of the Galerkin method in a multipole-accelerated program is only slightly more computationally expensive than the collocation method
Keywords :
Galerkin method; VLSI; boundary-elements methods; capacitance; circuit CAD; integrated circuit design; integrated circuit interconnections; permittivity; piecewise constant techniques; 3D structures; Galerkin techniques; IC interconnections; VLSI; arbitrary piecewise-constant dielectric medium; boundary element method; capacitance extraction; multiple dielectrics; multipole-accelerated capacitance extraction; Aging; Capacitance; Circuit optimization; Computer interfaces; Conductors; Coupling circuits; Dielectric constant; Dielectrics and electrical insulation; Integrated circuit interconnections; Moment methods;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Research in VLSI, 1995. Proceedings., Sixteenth Conference on
Conference_Location :
Chapel Hill, NC
Print_ISBN :
0-8186-7074-9
Type :
conf
DOI :
10.1109/ARVLSI.1995.515621
Filename :
515621
Link To Document :
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