VLSI architecture for repetitive waveform measurement with zero overhead averaging

The architecture and performance of a digital waveform acquisition instrument with built in averaging is discussed. The substantial time required for averaging in software was eliminated in the developed architecture by using hardware averaging at the speed of waveform occurrence, due to a fully pipelined operation of constituent units. This architecture was implemented using an FPGA development board, and was tested at a number of averages above 10,000 that should theoretically provide a reduction of the additive noise by more than 100 times. The effect of the noise reduction was clear from experiment. However, lower than predicted improvements were achieved when the level of the input noise before averaging was low. This occurred due to the quantization of the input signal, and should not be attributed to the averaging. Therefore, averaging of digitized data can impose particular limits on the achievable noise reduction but this only occurs when the noise level is very low and does not require much reduction per se.