Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications

This paper highlights the opportunities and challenges of III-V nanoelectronics for future high-speed, low- power digital logic applications. III-V materials in general have significantly higher electron mobility than Si and can potentially play a major role along with Si in future high-speed, low-power computing. The major potential advantage of using a III-V quantum-well field-effect transistor as a logic transistor is that it can be operated under very low supply voltage (e.g., 0.5 V), and hence, lower power dissipation while still achieving very high speed. Compared to other emerging high-mobility materials, such as, carbon nanotubes and semiconductor nanowires, which require "bottom-up" chemical synthesis for formation and suffer from the fundamental placement problem, III-V materials are far more practical in terms of patterning. However, many significant challenges remain to be overcome before III-V materials become applicable for future high-speed, low-power logic applications. These include: (i) finding a compatible high-K gate dielectric on III-Vs, (ii) demonstrating gate length scalability below 35 nm with acceptable I_ON/I_OFF ratio, (iii) improving the hole mobility in III-Vs or finding the right p-channel FET for the complementary metal-oxide-semiconductor (CMOS) configuration, and (iv) integrating III-V materials onto the Si substrate.