A packaged 43-Gb/s clock and data recovery IC

Author

Lao, Z. ; Guinn, K. ; Delaney, M. ; Jensen, J. ; Sokolich, M. ; Thomas, S. ; Fields, C.

Author_Institution

HRL Labs., Malibu, CA, USA

fYear

2005

fDate

30 Oct.-2 Nov. 2005

Abstract

A packaged 43-Gb/s clock and data recovery circuit with 1:2 demux in a 1μm InP SHBT technology is reported. A half-rate phase/frequency detector incorporating a four-phase LC-ring oscillator is implemented in the phase and frequency locked loop thus eliminating an external reference clock as a frequency acquisition aid. Measured pull-in and hold-in ranges are 0.9 GHz and 1.1 GHz, respectively, with a peak-to-peak clock jitter of 4.5 ps at 43-Gb/s input data rate.

Keywords

III-V semiconductors; clocks; demultiplexing equipment; frequency locked loops; heterojunction bipolar transistors; indium compounds; integrated circuit design; integrated circuit packaging; oscillators; phase locked loops; synchronisation; timing jitter; 0.9 GHz; 1 micron; 1.1 GHz; 1:2 demux; 4.5 ps; 43 Gbit/s; InP; SHBT technology; clock and data recovery IC; external reference clock; four-phase LC-ring oscillator; frequency acquisition aid; frequency detector; frequency locked loop; half-rate phase detector; input data rate; peak-to-peak clock jitter; phase locked loop; Circuit testing; Clocks; Frequency locked loops; Indium phosphide; Integrated circuit packaging; Jitter; Phase detection; Phase frequency detector; Sampling methods; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05. IEEE

Print_ISBN

0-7803-9250-7

Type

conf

DOI

10.1109/CSICS.2005.1531746

Filename

1531746