Title :
A modular pipelined macro-block for high-speed digital filtering applications
Author :
Gürkaynak, Frank K. ; Leblebici, Yusuf
Author_Institution :
Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., MA, USA
Abstract :
A programmable, fully pipelined macro-block (Aries), that can be used as a modular convolution engine to design digital FIR filters of any size with a minimum clock cycle of 20 ns is presented. The proposed module is very compact and occupies an active silicon area of less than 1.5 mm2 in a conventional 0.8 μm digital CMOS technology, allowing a large number of Aries macro-blocks to be easily embedded in a larger design to realize digital filters of any dimensions
Keywords :
CMOS digital integrated circuits; FIR filters; digital filters; high-speed integrated circuits; pipeline processing; programmable filters; 0.8 micron; 20 ns; Aries; CMOS technology; convolution engine; high-speed digital FIR filter; programmable modular pipelined macro-block architecture; silicon area; Application software; Arithmetic; CMOS technology; Clocks; Digital filters; Engines; Filtering; Finite impulse response filter; Signal processing; Silicon;
Conference_Titel :
Circuits and Systems, 1999. 42nd Midwest Symposium on
Conference_Location :
Las Cruces, NM
Print_ISBN :
0-7803-5491-5
DOI :
10.1109/MWSCAS.1999.867743
