Electronic testing for SOC designers

Author

Agrawal, Vishwani D.

Author_Institution

Agere Syst.

fYear

2002

fDate

2002

Firstpage

20

Abstract

Summary form only given. The presentation is divided into three parts. Part I contains definition of test and its motivation, test process and automatic test equipment (ATE), test economics and product quality, and fault modeling. Part II includes logic and fault simulation, testability measures, combinational and sequential ATPG, memory test, DSP-based analog test, model-based analog test, delay test, and IDDQ test. Part III covers scan design, built-in self-test (BIST), boundary scan, analog test bus, system test and testing of core-based designs

Keywords

VLSI; automatic test equipment; automatic test pattern generation; boundary scan testing; built-in self test; design for testability; fault simulation; integrated circuit testing; logic simulation; mixed analogue-digital integrated circuits; ATE; BIST; DSP-based analog test; IDDQ test; SoC designers; VLSI design; VLSI testing; analog test bus; automatic test equipment; boundary scan; built-in self-test; combinational ATPG; core-based design testing; delay test; design for testability; electronic testing; fault modeling; fault simulation; logic simulation; memory test; model-based analog test; product quality; scan design; sequential ATPG; system test; test economics; test process; testability measures; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Circuits and systems; Electronic equipment testing; Logic testing; Sequential analysis; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.

Conference_Location

Bangalore

Print_ISBN

0-7695-1441-3

Type

conf

DOI

10.1109/ASPDAC.2002.994877

Filename

994877