Architecture of a low-complexity non-binary LDPC decoder

In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC (NB- LDPC) codes, presented in [4]. To the knowledge of the authors this is the first implementation of an GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem of the NB-LDPC decoders, together with a significant complexity reduction per decoding iteration which becomes independent from the field´s order. The error decoding performance of the low complexity algorithm with proper compensation has been obtained through computer simulations. The frame error rate results are quite good with respect to the important complexity reduction. The results prove also that an implementation of a NB-LDPC decoder is now feasible and the extra complexity of the decoder is balanced by the superior performance of this class of codes. With their foreseen simple architectures and good-error correcting performances, NB-LDPC codes provides a promising vehicle for real-life efficient coding system implementations.