Title :
Dynamic noise analysis with capacitive and inductive coupling [high-speed circuits]
Author :
Choi, Seung Hoon ; Paul, Bipul C. ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
In this paper we propose a dynamic noise model to verify functional failures due to crosstalk in high-speed circuits. Conventional DC noise analysis produces pessimistic results because it ignores the fact that a gate acts as a low-pass filter. In contrast, the dynamic noise model considers the temporal property of a noise waveform and analyzes its effect on functionality. In this model, both capacitive and inductive coupling are considered as the dominant source of noise in high-speed deep-submicron circuits. It is observed that in the case of the local interconnects (where wire lengths are short), the effect of inductive coupling is small; however for long interconnects this effect may be considerable. Based on this noise model, we have developed an algorithm to verify high-speed circuits for functional failures due to crosstalk. The design of a 4-bit precharge-evaluate full adder circuit is verified, and many nodes which are susceptible to crosstalk noise are identified. It is observed and further verified by SPICE simulation that dynamic noise analysis is more realistic for verifying functional failures due to crosstalk than DC noise analysis
Keywords :
VLSI; capacitance; crosstalk; digital integrated circuits; equivalent circuits; failure analysis; high-speed integrated circuits; inductance; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; DSM circuits; capacitive coupling; crosstalk noise; deep-submicron circuits; dynamic noise analysis; dynamic noise model; full adder circuit; functional failures verification; high-speed circuits; inductive coupling; local interconnects; long interconnects; noise waveform temporal property; Adders; Analytical models; Circuit noise; Coupling circuits; Crosstalk; Failure analysis; Integrated circuit interconnections; Low pass filters; SPICE; Wire;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994887