Title :
A pipelined shared-memory architecture for FFT processors
Author :
Jia, Lihong ; Gao, Yonghorig ; Tenhunen, Hannu
Author_Institution :
ESDLab., R. Inst. of Technol., Stockholm, Sweden
Abstract :
This paper presented a VLSI-architecture for the FFT processors-which locally employed the pipelined architecture to realize the high speed radix-r Process Elements (PEs) and globally utilized the high-radix shared-memory architecture to implement the area-efficient FFT processors. Based on this architecture, a high performance 512-point FFT processor has been designed in the 0.6 um 3.3 v CMOS process to demonstrated its feasibility
Keywords :
CMOS digital integrated circuits; VLSI; digital signal processing chips; fast Fourier transforms; pipeline processing; shared memory systems; 0.6 micron; 3.3 V; CMOS chip; FFT processor; VLSI; high-speed high-radix processor element; pipelined shared memory architecture; CMOS process; Computer architecture; Delay effects; Fast Fourier transforms; Field-flow fractionation; Memory architecture; Signal processing; Signal processing algorithms; Silicon; Throughput;
Conference_Titel :
Circuits and Systems, 1999. 42nd Midwest Symposium on
Conference_Location :
Las Cruces, NM
Print_ISBN :
0-7803-5491-5
DOI :
10.1109/MWSCAS.1999.867757
