Implementation of high speed Reed-Solomon decoder

Author

Kim, Dong-Sun ; Choi, Jong-Chan ; Chung, Duck-Jin

Author_Institution

Syst.-IC Res. Center, KETI, KyungGi, South Korea

Volume

2

fYear

1999

fDate

1999

Firstpage

808

Abstract

Today the digital coded systems for either data transmission or data storage are much in common. The output of the channel or storage medium differs from its input because they are both sensitive to the errors that can result from impaired transmission. For that reason, Reed-Solomon (RS) codes are commonly used in various applications. In this paper, we propose the VLSI implementation of Reed-Solomon decoder with the development of an architecture featuring parallel and pipelined processing to improve the speed and low power design. We analyzed the RS decoding algorithm for the efficient parallel and pipelined structure and modified the Euclid´s algorithm arithmetic part to apply the parallel structure. The overall RS decoder is compared to Shuo´s. We show the 10% area efficiency increase over Shao´s time domain decoder and three times faster operation. In addition, we approve the proposed RS decoders with Altera FPGA Flex 10K-50, and Implemented with LG 0.6 processing

Keywords

Reed-Solomon codes; VLSI; decoding; field programmable gate arrays; high-speed integrated circuits; low-power electronics; pipeline processing; Altera FPGA Flex 10K-50; Euclid´s algorithm; VLSI implementation; area efficiency; high speed Reed-Solomon decoder; impaired transmission; low power design; parallel structure; pipelined processing; Algorithm design and analysis; Data communication; Decoding; Delay effects; Equations; Error correction codes; Memory; Polynomials; Reed-Solomon codes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1999. 42nd Midwest Symposium on

Conference_Location

Las Cruces, NM

Print_ISBN

0-7803-5491-5

Type

conf

DOI

10.1109/MWSCAS.1999.867758

Filename

867758