Synthesis of high performance low power dynamic CMOS circuits

This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, conventional logic design approaches cannot be used for Domino/Nora logic synthesis. To overcome this problem, we have used a new concept called unate decomposition of Boolean functions. However, two-level Domino/Nora realization for these functions are quite often not suitable for the realization of practical VLSI circuits having reasonable delay, because of the large number of series/parallel MOS transistors. To overcome this limitation, we have performed multilevel decomposition of each sub-function. The netlist produced by the multilevel decomposition directly maps (on-the-fly) to Domino/Nora cells. In order to analyze the circuits synthesized by our approach, we have estimated the delay and power of the circuits based on the models presented in the paper. Our result is then compared with the static CMOS circuits synthesized by standard SIS tool. Our approach has been found to achieve better results with regard to area, delay and power consumption compared to the existing approaches. It is envisaged that the synthesized Domino/Nora circuits will be suitable for realizing high-performance and low power circuits