DocumentCode
2405717
Title
A Clustered Flash Translation Layer for Mass Storage CompactFlash Systems
Author
Park, Kwanghee ; Kim, Deok-Hwan
Author_Institution
Sch. of Electr. Eng., Inha Univ. at Incheon, Incheon
fYear
2008
fDate
9-13 Jan. 2008
Firstpage
1
Lastpage
2
Abstract
This paper presents a novel flash translation layer design that uses clustered hash tables and two-level software cache technique to adaptively switch logical address from the host system to physical address in flash memory. The experimental results show that the proposed address translation mechanism provides good performance in address mapping and memory space requirement over the well-known NFTL and AFTL.
Keywords
cryptography; file organisation; flash memories; AFTL; NFTL; address mapping; clustered flash translation layer; clustered hash tables; flash memory; logical address; mass storage compact flash systems; memory space requirement; two-level software cache technique; Cache storage; Consumer electronics; File systems; Flash memory; Frequency; Humans; Microwave integrated circuits; Switches; Table lookup; Universal Serial Bus;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics, 2008. ICCE 2008. Digest of Technical Papers. International Conference on
Conference_Location
Las Vegas, NV
Print_ISBN
978-1-4244-1458-1
Electronic_ISBN
978-1-4244-1459-8
Type
conf
DOI
10.1109/ICCE.2008.4587962
Filename
4587962
Link To Document