DocumentCode
2405743
Title
Simulation and modelling of digital delay locked loops
Author
Aguiar, Rui L. ; Santos, Dinis M.
Author_Institution
Dept. de Electron. e Telecoms, Aveiro Univ., Portugal
Volume
2
fYear
1999
fDate
1999
Firstpage
843
Abstract
This paper discusses some results for simulation and modeling of charge-pump Delay Locked Loops (DLLs). A novel model based on a sampled-time approach is presented, and used for jitter analysis. The model is applied to input signal jitter, internally generated jitter and is further extended to handle jitter effects related with the control charge-pump. Behavior models for simulation purposes are derived from the theoretical model, and design considerations based on these are presented
Keywords
circuit simulation; delay lock loops; digital circuits; jitter; modelling; behavior models; charge-pump DLL; digital DLL; digital delay locked loops; input signal jitter; internally generated jitter; jitter analysis; modelling; sampled-time approach; simulation; Charge pumps; Circuits; Clocks; Delay lines; Detectors; Jitter; Phase detection; Phase locked loops; Semiconductor device modeling; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. 42nd Midwest Symposium on
Conference_Location
Las Cruces, NM
Print_ISBN
0-7803-5491-5
Type
conf
DOI
10.1109/MWSCAS.1999.867766
Filename
867766
Link To Document