Title :
Optimal dual-VT assignment for low-voltage energy-constrained CMOS circuits
Author :
Samanta, Debasis ; Pal, Ajit
Author_Institution :
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
Abstract :
In this paper we have addressed the problem of realizing dual-V T CMOS circuits for battery-operated hand held and portable systems. As the battery life is of primary concern, an algorithm is proposed to realize circuits with near minimal energy requirement in the standby mode as well as in the active mode, at the expense of some performance. An efficient algorithm for dual-VT assignment has been developed, which assigns high-VT to larger number of transistors compared to the existing approaches, leading to higher reduction in power. Experiments have been carried out to study the reduction in power requirement with the increase in delay (with corresponding increase in low-VT) compared to the highest performance single-VT realization. Our algorithm has been tested using standard ISCAS benchmark circuits. Experimental results have established that, by compromising small performance (5 to 10% increase in delay), it is possible to realize CMOS circuits using dual-V T technology with near-minimal energy requirement
Keywords :
CMOS integrated circuits; circuit optimisation; integrated circuit design; low-power electronics; active mode; battery-operated system; hand held system; low-power design; low-voltage energy-constrained CMOS circuit; optimal dual-VT assignment algorithm; portable system; power-delay product; standby mode; Batteries; CMOS technology; Circuit testing; Computer science; Constraint optimization; Delay; Power dissipation; Power engineering and energy; Subthreshold current; Threshold voltage;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994918
