• DocumentCode
    2406056
  • Title

    An evolutionary scheme for cosynthesis of real-time systems

  • Author

    Chakraverty, S. ; Ravikumar, C.P. ; Choudhuri, D. Roy

  • Author_Institution
    Netaji Subhas Inst. of Technol., New Delhi, India
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    251
  • Lastpage
    256
  • Abstract
    We consider the problem of hardware-software cosynthesis of application-specific embedded real-time systems. We assume that these systems are based on a heterogeneous multiprocessor architecture. One of the key problems in the synthesis of such systems is that of scheduling the real-time tasks. The conventional approach to the problem has been to use a task graph to describe the dependencies among tasks and to assign constant weights to the nodes and edges of the graph. The node weights represent task execution times and the edge weights represent communication times. However, in many real-time applications, the execution time and communication times cannot be determined a-priori. One can use the conventional task graph model in such situations by taking the worst-case times, but such an approach is necessarily pessimistic and wasteful in terms of resource utilization. We propose a model which treats the task execution times and communication times as stochastic variables with beta distributions. A stochastic task scheduling algorithm is presented which maximizes the probability of meeting all real-time constraints. A genetic algorithm, which employs the stochastic scheduling algorithm, is used for the synthesis of a high performance embedded system at minimum cost. We present experimental results for three task graphs
  • Keywords
    embedded systems; genetic algorithms; hardware-software codesign; multiprocessing systems; probability; processor scheduling; resource allocation; stochastic processes; timing; application-specific embedded real-time systems; beta distributions; communication times; constant weights; edge weights; embedded system synthesis; genetic algorithm; graph edges; graph nodes; hardware-software cosynthesis; heterogeneous multiprocessor architecture; hierarchical genetic algorithm; node weights; real-time applications; real-time constraints; real-time systems cosynthesis; real-time task scheduling; resource utilization; stochastic scheduling algorithm; stochastic task scheduling; stochastic task scheduling algorithm; stochastic variables; task allocation; task execution times; task graph; task graph model; Real time systems; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
  • Conference_Location
    Bangalore
  • Print_ISBN
    0-7695-1441-3
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2002.994931
  • Filename
    994931