Title :
A power minimization technique for arithmetic circuits by cell selection
Author :
Muroyama, Massnori ; Ishihara, Tohru ; Hyodo, A. ; Yasuura, IIiorto
Author_Institution :
Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan
Abstract :
As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper proposes a new design method, in which basic cells are selected from a set of circuits with different structures (symmetrical and asymmetrical) and connections to their terminals are exchanged, according to input-patterns to minimize power consumption. Experimental results for a parallel multiplier demonstrate average 30% power reduction
Keywords :
adders; circuit CAD; counting circuits; integrated circuit design; logic CAD; low-power electronics; multiplying circuits; parallel processing; 1 bit; adder; arithmetic circuits; asymmetrical structures; average power reduction; basic arithmetic circuit cell; basic cell selection; cell selection; circuit structures; component power consumption; counter; design method; input-patterns; low-power circuit design; parallel multiplier; power consumption; power consumption minimization; power minimization technique; symmetrical structures; terminal connections; Arithmetic; Circuits; Minimization; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994933
