DocumentCode :
2406168
Title :
Technological innovations to advance scalability and interconnects in bulk and SOI
Author :
Natarajan, Sreedhar ; Marshall, Andrew
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
fYear :
2002
fDate :
2002
Firstpage :
297
Lastpage :
298
Abstract :
With technology scaling rapidly, there is increased need for improved performance. While improved performance can be achieved with lower threshold voltages, leakage will be a major issue at technologies below 0.1μm. Interconnect scaling is not expected to keep up with component scaling, resulting in higher capacitance losses and challenges in signal routing. We consider how scaling will impact design for low power and high performance applications. SOI may be a solution for some issues like SER due to the presence of buried oxide. Performance can be enhanced by SOI technology due to the absence of junction capacitance. The combination of short gate length technologies and PD-SOI can mitigate performance degradation due to interconnect capacitances and leakage
Keywords :
doping profiles; integrated circuit interconnections; large scale integration; radiation hardening (electronics); silicon-on-insulator; PD-SOI; Si; interconnect capacitances; interconnect scaling; junction capacitance; leakage; performance; short gate length technologies; soft errors; stacked SOI; transistor doping profiles; CMOS technology; Capacitance; Immune system; Impact ionization; Resistors; Routing; Scalability; Silicon on insulator technology; Technological innovation; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
Type :
conf
DOI :
10.1109/ASPDAC.2002.994937
Filename :
994937
Link To Document :
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