Novel ultra low-leakage power circuit techniques and design algorithms in PD-SOI for sub-1 V applications

As supply voltage and technology are scaled, leakage power becomes significant in CMOS ICs. This paper proposes and analyzes new circuit styles in PD-SOI technology which reduce standby power in the sub-1 V regime by over three orders of magnitude while maintaining circuit speed with minimal overhead. Simulation results obtained using process parameters from an IBM 0.13 μm PD-SOI technology show considerable improvement over previously proposed methods as supply voltage is scaled to 0.5 V. It also proposes a definitive design guideline for implementing such schemes.