Title :
A reduced clock swing domino gate in SOI
Author :
Casu, M.R. ; Gelmi, M. ; Masera, G. ; Piccinini, G. ; Zamboni, M.
Author_Institution :
Dept. of Electron., Politecnico di Torino, Italy
Abstract :
The authors have introduced a domino gate that operates at a reduced clock swing. Using a DTMOS, the performance degradation is minimal while the total power consumption is greatly reduced since the clock tree has a halved voltage swing. Due to the squared relationship between voltage and power, 75% saving can be obtained on a clock whose contribution can be up to 50% of the overall power consumption. The use of active body-biasing circuits yields an order of magnitude reduction of the gate leakage power dissipation.
Keywords :
MIS devices; MOS integrated circuits; SPICE; digital simulation; integrated circuit modelling; leakage currents; logic gates; semiconductor device models; silicon-on-insulator; DTMOS footer; SOI; active body-biasing circuits; gate leakage power dissipation; modified two ways OR gate; performance degradation; reduced clock swing domino gate; simulation; total power consumption reduction; Integrated circuit modeling; Leakage currents; MIS devices; MOS integrated circuits; SPICE; Semiconductor device modeling; Silicon on insulator technology;
Conference_Titel :
SOI Conference, IEEE International 2002
Print_ISBN :
0-7803-7439-8
DOI :
10.1109/SOI.2002.1044430
