Impact of technology scaling on metastability performance of CMOS synchronizing latches

In this paper, we use circuit simulations to characterize the effects of technology scaling on the metastability parameters of CMOS latches used as synchronizers. We perform this characterization by obtaining a synchronization error probability curve from a histogram of the latch delay. The main metastability parameters of CMOS latches are τ_m and T_w. τ_m is the exponential time constant of the rate of decay of metastability and T _w is effective metastability window size at a normal propagation delay. Both parameters can be extracted from a histogram of the latch delay. This paper also explains a way to calibrate the simulator for accuracy. The simulations indicate that τ_m scales better than the technology scale factor. T_w also scales down but its factor cannot be estimated as well as that of τ _m. This is because T_w is a complex function of signal and clock edge rate and logic threshold level