A completely integrated low jitter CMOS PLL for analog front ends in system on chip environment

Describes the PLL designed for the analog front-end of the silicon tuner in the cable modem system. The PLL is used to generate clocks (150-175 MHz) for the DAC and hence the phase noise (jitter) requirement is very aggressive. Low noise design for all the main blocks was a key to achieve this. Care was taken to reduce reference spurs and supply/substrate injected spurs. The PLL uses two supplies. Charge pump and voltage controlled oscillator (VCO) work off a 3.3 V analog supply as it can give maximum VCO control voltage compliance, which helps reduce VCO gain, and hence reference and supply/substrate induced spurs. The digital part works off 1.8 V supply as 1.8 V core transistors give fastest switching which reduces phase noise in the dividers. The 3.3 V to 1.8 V interfaces have been optimized for the desired edges of output clock and phase comparison clock so that they have minimum contribution to phase error. Optimum loop bandwidth, PSRR and supply filtering were achieved to minimize phase noise and spurious modulation