Perspectives of fully-depleted SOI transistors down to 20nm gate length

Author

Luyken, R.J. ; Städele, M. ; Rösner, W. ; Schulz, T. ; Hartwich, J. ; Dreeskornfeld, L. ; Risch, L.

Author_Institution

Corporate Res., Infineon Technol. AG, Munich, Germany

fYear

2002

fDate

7-10 Oct 2002

Firstpage

137

Lastpage

139

Abstract

Device simulations have been carried out for n-channel fully depleted SOI transistors with undoped channels and single gates. Si body thickness, lateral gradient of the doping concentration profiles in source and drain, and spacer width have been varied to explore the design space. Gate lengths, gate oxide thicknesses, and operating voltages were chosen for three technology nodes (90, 65, and 45 nm) according to the specifications of the International Technology Roadmap for Semiconductors (ITRS 2001).

Keywords

MOSFET; doping profiles; semiconductor device models; silicon-on-insulator; 20 nm; 45 nm; 65 nm; 90 nm; ITRS 2001; Si; Si body thickness; device simulations; doping concentration profiles; fully-depleted SOI transistors; gate lengths; gate oxide thicknesses; lateral gradient; operating voltages; single gates; spacer width; undoped channels; MOSFETs; Semiconductor device modeling; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, IEEE International 2002

Print_ISBN

0-7803-7439-8

Type

conf

DOI

10.1109/SOI.2002.1044450

Filename

1044450

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2406597