DocumentCode :
2406610
Title :
Tendency for full depletion due to gate tunneling current
Author :
Wan, Hui ; Fung, Samuel K H ; Su, Pin ; Chan, Mansun ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear :
2002
fDate :
7-10 Oct 2002
Firstpage :
140
Lastpage :
142
Abstract :
A high gate tunneling current level from ultra-thin gate dielectrics leads to a tendency of full depletion. By studying the hole concentration profile under the worst case scenario with Vg = -Vdd, a method of categorizing ultra thin film SOI MOSFETs is proposed. A design analysis of FD SOI device using this method is demonstrated.
Keywords :
MOSFET; hole density; silicon-on-insulator; tunnelling; design analysis; full depletion; gate tunneling current; hole concentration; ultra thin film SOI MOSFETs; ultra-thin gate dielectric; Charge carrier density; MOSFETs; Silicon on insulator technology; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, IEEE International 2002
Print_ISBN :
0-7803-7439-8
Type :
conf
DOI :
10.1109/SOI.2002.1044452
Filename :
1044452
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2406610
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