Title :
An efficient 3-bit-scan multiplier without overlapping bits, and its 64×64 bit implementation
Author :
Yu, Hak-Soo ; Abraham, Jacob A.
Author_Institution :
Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA
Abstract :
In this paper, we present an efficient 3-bit-scan multiplier without overlapping bits which has good power-delay area trade-offs. Generation of partial product terms in this multiplier is performed in parallel with the multiplication operation. Parallel partial product generation results in a multiplier which is faster than conventional sequential multipliers. The architecture of the 3-bit-scan multiplier without overlapping bits is therefore suitable for synchronous sequential multipliers which are required to operate at low power and at relatively high speed for their area
Keywords :
integrated circuit design; logic design; multiplying circuits; parallel architectures; sequential circuits; 3 bit; high speed operation; low power operation; multiplication operation; multiplier; multiplier architecture; multiplier implementation; overlapping bits; parallel partial product generation; partial product terms; power-delay-area trade-offs; sequential multipliers; synchronous sequential multipliers; three-bit-scan multiplier; Costs; Footwear industry; Jacobian matrices; Logic; Personal digital assistants; Power engineering and energy; Power engineering computing; Read only memory; Signal processing; Signal processing algorithms;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994960