Architecture and design of a high performance SRAM for SOC design

Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropriate circuit partitioning, transistor sizing, choice of a suitable sense amplifier, a good resetting technique and judicial use of dual V_th transistors, we have achieved a high speed memory without dissipating too much power. We begin by giving the specifications of the memory that was the design target. We then describe the key design techniques. Finally, we present the implementation on a test chip, and silicon measured results, which (we believe) to be the best in class of embedded SRAM compliers available from various vendors in the world at the time of writing this paper. Also, this architecture has achieved yields well over 95% in 0.18 μm technology