DocumentCode
2406814
Title
A novel method to improve the test efficiency of VLSI tests
Author
Cui, Hailong ; Seth, Sharad C. ; Mehra, S.K.
Author_Institution
Dept. of Comput. Sci. & Eng., Nebraska Univ., Lincoln, NE, USA
fYear
2002
fDate
2002
Firstpage
499
Lastpage
504
Abstract
Considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal of minimizing the test cost. Best and worst case bounds are established for the performance of a reordered sequence compared to the original sequence of test application. SEMATECH test data and simulation results are used throughout to illustrate the ideas
Keywords
VLSI; automatic test pattern generation; circuit optimisation; circuit simulation; fault simulation; integrated circuit testing; SEMATECH; VLSI tests; best case bounds; defect coverage; reordered sequence; simulation results; test application cost; test efficiency; test reordering; test vector permuting; worst case bounds; Automation; Compaction; Computer science; Cost benefit analysis; Cost function; Design for testability; Fabrication; Silicon; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location
Bangalore
Print_ISBN
0-7695-1441-3
Type
conf
DOI
10.1109/ASPDAC.2002.994969
Filename
994969
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