• DocumentCode
    2406875
  • Title

    A timing exception technique for SOI circuits

  • Author

    Kuang, J.B. ; Chuang, C.T. ; Saccamango, M.J.

  • Author_Institution
    Adv. Server Dev., IBM Corp., Rochester, MN, USA
  • fYear
    2002
  • fDate
    7-10 Oct 2002
  • Firstpage
    173
  • Lastpage
    175
  • Abstract
    In this paper, we present a technique that ensures the functionality and timing consistency in SOI circuits while simultaneously attaining performance leverage. It addresses cycle-dependent, particularly initial-cycle, speed and noise concerns due to the parasitic bipolar current and hysteretic Vt variation associated with the PD/SOI technology.
  • Keywords
    VLSI; silicon-on-insulator; timing circuits; SOI circuits; VLSI design; functionality; hysteretic Vt variation; parasitic bipolar current; timing consistency; timing exception technique; Silicon on insulator technology; Timing circuits; Very-large-scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, IEEE International 2002
  • Print_ISBN
    0-7803-7439-8
  • Type

    conf

  • DOI
    10.1109/SOI.2002.1044465
  • Filename
    1044465
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2406875