Title :
Constraint driven pin mapping for concurrent SOC testing
Author :
Huang, Yu ; Mukherjee, Nilanjan ; Tsai, Chien-Chung ; Samman, Omer ; Zaidan, Yahya ; Zhang, Yanping ; Cheng, Wu-Tung ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
A solution for mapping core I/O pins to system-on-a-chip (SOC) I/O pins in order to achieve cost-efficient concurrent test for core-based designs is presented in this paper. The problem of pin mapping is first formulated as two well-known NP-complete problems. A heuristic algorithm is then proposed to determine a solution. The objectives driving this solution are geared towards reducing the total number of SOC pins needed and satisfying the test constraints specified by core integrators. Experimental results demonstrate the efficiency of the proposed method
Keywords :
application specific integrated circuits; automatic testing; circuit optimisation; computational complexity; concurrent engineering; integrated circuit testing; logic testing; NP-complete problems; constraint driven pin mapping; core I/O pins; cost-efficient concurrent test; heuristic algorithm; pin mapping; system-on-a-chip I/O pins; test constraints; Built-in self-test; Energy consumption; Integrated circuit testing; Job shop scheduling; Logic testing; Manufacturing; Power dissipation; Power system modeling; Protocols; Resource management;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.994971
