Title :
Reformatting test patterns for testing embedded core based system using test access mechanism (TAM) switch [SoC]
Author :
Basu, Subhayu ; Mukhopadhay, Debdeep ; Roychoudhury, D. ; Sengupta, I. ; Bhawmik, S.
Abstract :
In this paper, a new algorithm for reformatting the test vector of system on chip (SOC) with test access mechanism (TAM) has been proposed. Exhaustive experimentation has been conducted by employing random reformatted test vectors for a variety of SOCs, constructed with the ISCAS sequential benchmark circuits. For a limited number of input pins, which have been provided for testing the SOC, the proposed algorithm drastically reduces the test-time as well as the hardware
Keywords :
integrated circuit testing; logic testing; sequential circuits; test equipment; ISCAS sequential benchmark circuits; SoC; SoC testing; TAM switch; embedded core based system testing; input pins; random reformatted test vectors; system on chip; test access mechanism switch; test hardware; test pattern reformatting; test vector reformatting algorithm; test-time; Bandwidth; Benchmark testing; Circuit testing; Pins; Rails; Sequential analysis; Switches; System testing; System-on-a-chip; Test pattern generators;
Conference_Titel :
Design Automation Conference, 2002. Proceedings of ASP-DAC 2002. 7th Asia and South Pacific and the 15th International Conference on VLSI Design. Proceedings.
Conference_Location :
Bangalore
Print_ISBN :
0-7695-1441-3
DOI :
10.1109/ASPDAC.2002.995001
